The present invention relates to digital counter circuits and, more particularly, to digital binary counter circuits.
A digital binary counter circuit is a logic circuit used for counting the number of times a particular event has occurred with respect to a base clock signal (CLK). A counter may be any arbitrary length (i.e., up to n-bits in length), with the maximum number of countable events being related to the counter bit length. For example, an 8-bit counter can count up to 256 events (i.e., up to 28), while a 16-bit counter can count up to 65,536 events (i.e., up to 216), etc.
Counter circuits are used in many integrated circuit designs, for example in an System on Chip (SoC), and may be formed of a set of sequential elements, such as flip-flops, operatively coupled together with suitable combinatorial control logic. As more features are being integrated into digital circuits, such as SoCs, the number of flip-flops used for the counter circuit portions, and therefore the amount of control logic used, is increasing. Furthermore, higher throughput necessitates operating such digital counters at ever higher frequencies. All this leads to a significant increase in dynamic power consumption of digital counters, or limited operational frequencies.